The present invention relates to a comparator that compares a first voltage applied to a first input to a second voltage applied to a second input, and delivers an output signal having a first value when the second voltage is higher than the first voltage and having a second value when the second voltage is lower than the first voltage.
In certain applications, it may prove necessary to compare a supply voltage with a determined voltage. This comparison cannot be carried out with a prior art comparator having two inputs and one power supply input. The resulting arrangement is schematically represented in FIG. 1.
The prior art comparator represented in this figure receives a supply voltage at its supply terminal and one of its inputs, for example, its positive input. It receives at its other input, here the negative input, a voltage Vps to be compared to the voltage Vcc. It will be understood by those skilled in the art that this arrangement cannot operate since the differential stages of the comparator cannot be biased by the same voltage as one of the voltages to be compared.
In view of the foregoing background, an object of the present invention is to provide a comparator that allows two voltages to be compared, wherein at least one of the voltage is a supply voltage of the comparator.
The present invention advantageously provides a comparator allowing two voltages to be compared without requiring a third voltage distinct from the two voltages to be compared.
Another object of the present invention is to use this comparator to manage the supply voltage of an integrated circuit.
FIG. 2 schematically represents a prior art power supply management system. An integrated circuit IC comprising a distribution line 20 of an internal supply voltage Vps and a receiving terminal 21 of an external supply voltage Vcc can be distinguished. The line 20 is linked to the terminal 21 through a diode D1 biased in the forward direction. The line 20 is also linked to the output of a booster circuit, such as a charge pump PMP, for example, controlled by a regulator REG. The regulator activates the charge pump PMP when the voltage Vps becomes lower than a threshold Vmin, so as to maintain the latter proximate to this threshold. The charge pump is therefore activated when the voltage Vcc is lower than Vmin+Vd. Vd is the voltage drop at the terminals of the diode (threshold voltage of the diode), which is typically on the order of 0.7 to 1 V according to the technology used.
Since the consumption of a charge pump, and generally speaking that of a booster circuit, are significant, it is desirable to delay the moment when the charge pump is activated by removing the diode voltage Vd. If the diode voltage Vd is zero, the voltage Vcc ensures the power supply of the line 20 until the voltage Vcc becomes lower than Vmin. In this case, the charge pump remains deactivated in the range of values (Vmin, Vmin+Vd) of the voltage Vcc.
Thus, another aspect of the present invention is to provide a management system of the supply voltage of an integrated circuit using a comparator to compare the internal supply voltage and the external supply voltage of the integrated circuit.
This and other objects, advantages and features in accordance with the present invention are provided by a comparator arranged to compare a first voltage applied to a first input of the comparator and a second voltage applied to a second input of the comparator, and to deliver to one output of the comparator an output signal having a first value when the second voltage is higher than the first voltage and having a second value when the second voltage is lower than the first voltage.
The comparator comprises first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator to receive the first voltage. The second PMOS transistor has its source connected to the second input of the comparator to receive the second voltage. The output of the comparator is connected to the drain of one of the transistors.
The gates of the first and the second transistors may be interconnected. A transistor may have its gate linked to its drain, and the output of the comparator is linked to the drain of the other transistor. The bulk of the first PMOS transistor may be linked to the source of the first transistor to receive the first voltage, and the bulk of the second PMOS transistor is may be linked to the source of the second transistor to receive the second voltage. The PMOS transistors may have gates of the same dimension.
The comparator may comprise a first branch comprising the first PMOS transistor in series with a first source of current, and a second branch comprising the second PMOS transistor in series with a second source of current. The sources of current provide substantially equal or proportional currents in the first and second branches.
The first branch may further comprise the first PMOS transistor in series with a first NMOS transistor. The second branch may further comprise the second PMOS transistor in series with a second NMOS transistor. The drain of the first PMOS transistor may be linked to the drain of the first NMOS transistor. The drain of the second PMOS transistor may be linked to the drain of the second NMOS transistor. The gates of the first and second NMOS transistors may be linked to the output of a reference voltage generator providing substantially equal or proportional currents in each of the branches.
The present invention also relates to an integrated circuit comprising a comparator according to the present invention arranged to compare an external supply voltage of the integrated circuit and an internal supply voltage of the integrated circuit.
The integrated circuit may comprise a distribution line of the internal supply voltage linked to a booster circuit and to a receiving terminal of the external supply voltage through a power switch driven by the output signal of the comparator.
The integrated circuit may also comprise means for triggering the booster circuit when the internal supply voltage is lower than a determined threshold, so as to maintain the internal supply voltage proximate to the threshold when the external supply voltage is too low. The power switch may be blocked by the comparator when the booster circuit is active.
The power switch may be a PMOS transistor receiving the output signal of the comparator at its gate. The booster circuit may be a charge pump. The integrated circuit may comprise a memory array comprising electrically erasable and programmable memory cells, and at least one line decoder having a supply terminal connected to the distribution line of the internal supply voltage.
The determined threshold is higher than or equal to the sum of a memory cell read voltage and a MOS transistor threshold voltage. The integrated circuit comprises a single booster circuit and a regulator with two modes of operation. One operation, during phases of erasing or programming memory cells, takes the internal supply voltage to a high erasing or programming voltage. A second operation, at least during phases of reading memory cells, maintains the internal supply voltage proximate to the determined threshold when the external supply voltage is too low.